In the modern communication industry there is often a need to determine associative relationships between data elements. In order to meet this need, a content addressable memory (CAM) is used to make a comparison of an input data value and a stored data value in the CAM cell. For example, a CAM cell array contained within a network router would determine whether there is an association between the address in the packet header and the addresses of the computers in the network. In determining the association, a search and comparison method must be performed between the address in the packet header and all the addresses in the network. This search and comparison is both time and resource intensive using traditional solutions involving convenient RAM-technology. Contrary to that, CAM-technology provides much faster search and compare operations.
More particularly, a CAM is a memory device with two modes of access. In one mode, the CAM works as a normal random access memory, wherein the contents of the memory are read and written at specified addresses. In a second mode, the CAM compares the specified string, often called the comparand with the information stored in its memory cells and then generates signals which indicate if a match between the comparand and any of the information in the memory was found.
Typical circuitry of a 10 transistor-SRAM based CAM-cell includes a standard 6 Transistor-SRAM cell for storage and a 4 Transistor-comparator. Both of these functions use a relatively large area because of the large number of devices connected on very few internal nodes (need for several metal levels to insure interconnections as for instance each storage node is connected to 6 transistors, only 2 adjacent devices can be efficiently connected together without area consuming interconnections). Additionally, a very poor balance between the number of P-channels (2T) and N-channels (8T) forces an imperfect layout with some empty spots. Typically, such circuitry requires much area per memory cell.
In view of the above, there is a need to provide a CAM cell allowing a further memory cell size down-scale as compared to conventional CAM cells.